1. Field of the Invention
The invention relates generally to the field of computer science. More particularly, the invention relates to software. Specifically, a preferred implementation of the invention relates to an interconnect model compiler.
2. Discussion of the Related Art
The design of new integrated circuits is becoming increasingly expensive. As the total number of devices in a chip increases, the design calculations become more complex and time consuming to solve. New integrated circuits take longer to design due to increased CPU requirements for design and verification, thereby increasing the time-to-market. Therefore, what is required is an approach that makes the design of increasingly complex integrated circuit designs less time consuming and, therefore, less expensive.
The cost of failure for each prototype chip that does not perform as intended is also increasing. More complex integrated circuits are requiring more complex and costly fabrication systems. Many of the fabrication tools and processes are design specific. What is also required, therefore, is an approach that makes the design of increasingly complex integrated circuits designs more reliable.
Meanwhile, the increasing density of the designs is driving a reduction in power supply voltage. However, the lower supply voltage requires a more accurate design since the thresholds must be closer. Therefore, what is also required is an approach the makes the design of increasingly complex integrated circuits designs more accurate.
Prior art logic synthesis tools for designing integrated circuits are well known to those skilled in the art. For instance, a static timing analyzer is typically used during the integrated circuit design process to validate and/or optimize the speed of an integrated circuit design of interest.
The static timing analyzer performs calculations based, at least in-part, on data from a standard cell library. The electrical properties of the components that compose the design are represented by the standard cells. The static timing analyzer can be equipped to interface using an open library API (OLA).
A problem with this technology has been that as microelectronics have become smaller, features of the design not represented by the standard cells have become more important. For example, in very deep submicron (VDSM) technology the interconnects between the standard cells exhibit increased parasitic properties. Therefore, what is also required is an approach that takes the electrical properties of the interconnects into account.
Heretofore, the requirements of speed, reliability and accuracy with respect to design and taking into account the electrical properties of the interconnects have not been fully met. What is needed is a solution that addresses all of these requirements, preferably simultaneously.
A goal of the invention is to satisfy the above-discussed requirement of increased design speed. Another goal of the invention is to satisfy the above-discussed requirement for improved design reliability. Another goal of the invention is to satisfy the above-discussed requirement for increased design accuracy. Another goal of the invention is to satisfy the above-discussed requirement for taking into account the electrical properties of the interconnects. Another goal of the invention is enabling customers to embed their algorithms into existing design flow to achieve design sign-off.
One embodiment of the invention is based on a method of compiling a circuit interconnect model, comprising: providing extraction data from an interconnect; reading a dataset from said extraction data from said interconnect; translating said dataset to form a model; evaluating said model for a set of conditions to obtain a solution; and writing said solution to an application. Another embodiment of the invention is based on an electronic media, comprising a program for performing this method. Another embodiment of the invention is based on a computer program, comprising computer or machine readable program elements translatable for implementing this method. Another embodiment of the invention is based on an integrated circuit designed in accordance with this method. Yet another embodiment of the invention is based on a computer program comprising computer program means adapted to perform the steps of providing extraction data from an interconnect; reading a dataset from said extraction data from said interconnect; translating said dataset to form a model; evaluating said model for a set of conditions to obtain a solution; and writing said solution when said program is run on a computer.
These, and other, aspects of the invention will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. It should be understood, however, that the following description, while indicating preferred embodiments of the invention and numerous specific details thereof, is given by way of illustration and not of limitation. Many changes and modifications may be made within the scope of the invention without departing from the spirit thereof, and the invention includes all such modifications.